This invention relates generally to computer memory organization and, more particularly, to the organization of a stack memory composed of charge coupled device shift registers and capable of last-in-first-out or first-in-first-out operation. While the invention in its broad aspects may find application in other charge storage memories where refreshing of stored charge is required such as well-known MOS shift registers, the invention is particularly directed to a charged coupled device embodiment.
Charge coupled device shift registers are well-known in the art as shown by U.S. Pat. No. 3,758,794 issued to W. F. Kosonocky on Sept. 11, 1973. In such registers, information is stored as the presence or absence of charge packets of minority carriers in storage cells beneath the electrodes of the register. These packets of minority carriers are initially injected into a register from a source diffusion and are shifted from one electrode to the next by varying the voltage on the register electrodes. Various arrangements for varying the electrode voltage and clocking the registers are possible, using two, three or four phase voltages. Information clocked into the last storage cell of a register may be detected, or it may be transmitted to another register by means of a floating diffusion located between the last register storage cell and a drain diffusion. The purpose of the drain diffusion is to remove the charge packets after the information they represent has been transmitted or detected.
Such shift registers have suggested themselves as particularly suited to stack memory designs. In the past, serial stack memories of the last-in-first-out or first-in-first-out kind have been widely used in computer systems. They have often been carved out of random access memories by software programs, thus complicating the task of the programmer. In other cases, hardware embodiments of stack memories have been built from MOS and other semi-conductor memory structures. However, because of the simplicity and physical size of charge coupled devices, a stack-memory utilizing them and constructed according to an efficient organization plan has many advantages over prior art hardware embodiments. In particular, reduced fabrication costs and increased storage capacity per integrated circuit chip result.
When using charge coupled devices in memory applications, it is necessary to periodically refresh the memory. Otherwise, thermal and other generation of minority carriers cause impairment of the memory contents. In addition, charge transfer inefficiencies require that after a certain number of charge transfers, the charge be regenerated.
Prior art devices have offered several solutions to the refreshing problem. In one, the data of the memory is shifted out of the memory, temporarily stored and then shifted back. Such an approach is overly complicated, wasteful of space and unsuited to stack memory applications. Another method, used particularly in conjunction with charge coupled device shift register structures, involves connecting a shift register or a series of them in a continuous loop through which the stored data is continuously circulated. During this circulation, the data passes through regeneration means, such as the floating diffusion arrangement previously discussed. Such a technique does not lend itself to a simple organization of a last-in-first-out or a first-in-first-out stack where it is desired that the data be maintained in a particular order at all times so that the first or last data items are immediately accessible.
The problem of organizing an efficient structure for refreshing data and transferring data between shift registers in a charge coupled device stack memory is further complicated by a competing concern for minimizing the size of the memory. Two phase charged coupled device structres are simpler and result in a space saving of approximately 20% over three or four phase structures. Translated into integrated circuit terminology, two phase structures result in reduced on-chip complexity and higher bit density per chip. Therefore, to obtain the maximum advantage from using charge coupled device shift registers, it is highly desirable to use two phase structures. However, these structures inherently transfer data unidirectionally, while bidirectional capability is necessary to avoid complicated structure in a serial stack memory designed to operate in either last-in-first-out or first-in-first-out modes. The prior art has not provided a transfer and refresh organization which adpats unidirectional shift registers to bidirectional data transfer while avoiding continuous loop data regenerating schemes.